国際会議(査読付き)

平成28年度 (2016年度)

  1. K. Endo, S. Nagamine, W. Saito, T. Matsudai, T. Ogura, T. Setoya, and K. Nakamae, “Direct Photo Emission Motion Observation of Current Filaments in the IGBT under Avalanche Breakdown Condition,” The 28th IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD 2016), pp. 367–370, 2016.

平成26年度 (2014年度)

  1. K. Endo, K. Norimatsu, K. Nakashima, T. Setoya, S. Nagamine, T. Nakamura, K. Koshikawa, and K. Nakamae, “Time resolved emission observation from top surface in avalanche breakdown of power MOSFET,” in Proc. IEEE International Reliability Physics Symposium (IRPS), Hawaii, USA. pp. FA–3, 1–5 Jun. 2014.
  2. Y. Midoh, R. Nishi, M. N. Shirazi, Y. Kamakura, Y. Inoue, J. Miura, and K. Nakamae, “HawkC: computer-aided 3D visualization and analysis software for electron tomography,” in Proc. 18th International Microscopy Congress (IMC),Prague, Czech Republic, 7-12 Sep. 2014.

平成25年度 (2013年度)

  1. S. Kudo, Y. Hirose, K. Funayama, K. Ohgata, M. Inoue, K. Eguchi, A. Nishida, K. Asayama, N. Hattori, T. Koyama, and K. Nakamae, "Atomic-level study of TDDB mechanism of Hf-doped SiON gate dielectrics using Cs-corrected STEM and atom probe tomography," in Proc. IEEE International Reliability Physics Symposium (IRPS), Monterey, USA, 5B-2, 14-18 April 2013.
  2. N. Fukuda, S. Sakaguchi, and K. Nakamae, "Dependence of quantum error correction criteria on concentration of qubits in an ion-trap quantum computer," in Proc. SPIE Defense, Security, and Sensing, Baltimore, USA, vol.8749, p.87490L, 2-3 May 2013.
  3. K. Miura, Y. Soga, K. Nakamae, K. Kadota, T. Aritake, and Y. Yamazaki, "Fast and accurate design based binning based on hierarchical clustering with invariant feature vectors for BEOL," in Proc. 24th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp.7-12, 13-16 May 2013.
  4. S. Kudo, Y. Hirose, K. Funayama, M. Inoue, A. Nishida, N. Hattori, T. Koyama, and K. Nakamae, "Study of Hf-doped SiON gate dielectrics by using atom probe tomography," in Proc. JSAP-MRS Joint Symposia, Kyoto, JAPAN, 17p-M7-7, 16-20 Sep. 2013.
  5. Y. Midoh, A. Osaki, and K. Nakamae, "A shape-modification strategy of electron beam direct writing considering circuit performance in LSI interconnects," in Proc. SPIE Advanced Lithography, San Jose, USA, 9049-68, 23-27 Feb. 2014.

平成24年度 (2012年度)

平成23年度 (2011年度)

  1. K. Nikawa, M. Yamashita, T. Matsumoto, K. Miura, Y. Midoh, and K. Nakamae, "Invited: The combinational or selective usage of the laser squid microscope, the non-bias laser terahertz emission microscope, and fault simulations in non-electrical-contact fault localization," Proc. 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, Microelectronics Reliability, vol. 51, no. 9-11, pp. 1624-1631 (3-7 Oct. 2011).

平成22年度 (2010年度)

  1. T. Notsu, K. Miura, K. Nakamae, "Enhancement of Defect Tolerance in the QCA-based Programmable Logic Array (PLA)," Nanotech Conference & Expo 2010, pp. 29- 32, Anaheim, CA, USA (June 21-24, 2010).
  2. M. Yamashita, C. Otani, T. Matsumoto, Y. Midoh, K. Miura, K. Nikawa, K. Nakamae, and M. Tonouchi, "Non-bias inspection of electrical failures in LSI interconnects using LTEM prototype system," The 35th International Conference on Infrared, Millimeter and THz Waves (IRMMW-THz 2010), Mo-P.60, Rome, Italy (September 5-10, 2010).
  3. Y. Midoh, F. Hayashi, K. Nakamae, "Three-dimensional reconstruction from microscope tilt-series images using object tracking based on particle filter," The 17th International Microscopy Congress (IMC17), M17.5, Rio de Janeiro, Brazil (September 19-24 2010).

平成21年度 (2009年度)

  1. M. Yamashita, C. Otani, S. Kim, H. Murakami, M. Tonouchi, T. Matsumoto, Y. Midoh, K. Miura, K. Nakamae and K. Nikawa, "Development of an LTEM prototype system for LSI failure analysis," in Proc. 34rd International Conference on Infrared, Millimeter and Terahertz Waves (IRMMWTHz), Seoul, Korea, T2D01.0155 (26–27 Sep. 2009).
  2. K. Nikawa, M. Yamashita, C. Otani, M. Tonouchi, H. Murakami, S. Kim, K. Nakamae, K. Miura, Y.Midoh, T. Matsumoto, Y. Aoki, T. Nagaishi, S. Inoue, and T. Sakai, "Novel electrical failure analysis tools for LSI chips: non-bias and non-signal-application," in Proc. Japan-Taiwan Microelectronics International Symposium, Tokyo, Japan (Oct. 2009).
  3. M. Yamashita, C. Otani, S. Kim, H. Murakami, M. Tonouchi, T. Matsumoto, Y. Midoh, K. Miura, K. Nakamae, and K. Nikawa, "Laser terahertz emission microscope for inspecting interconnect defects in semiconductor devices," in Proc. 20th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF2009), Arcachon, France (5–9 Oct. 2009).
  4. S. Kobayashi, S. Kyoh, T. Kotani, Y. Takekawa, S. Inoue and K. Nakamae, "Full-chip layout optimization for process margin enhancement using model-based hot-spot fixing system," in Proc. 22nd International Microprocesses and Nanotechnology Conference (MNC 2009), Sapporo, Japan (16–19 Nov. 2009).
  5. M. Yamashita, C. Otani, S. Kim, H. Murakami, M. Tonouchi, T. Matsumoto, Y. Midoh, K. Miura, K. Nakamae, and K. Nikawa, "Development of an LTEM prototype system for LSI failure analysis," in Extended Abstracts of 2nd International Workshop on Terahertz Technology (TeraTech 09), Osaka, Japan, pp. 261–262 (30 Nov.–3 Dec. 2009) .
  6. Y. Midoh, T. Terasaka, and K. Nakamae, "Evaluation of maskless electron-beam direct writing with double character projection apertures," in Proc. SPIE: Alternative Lithographic Technologies II, San Jose, USA, vol. 7637, 7637-12 (21–25 Feb. 2010).
  7. S. Kobayashi, S. Tanaka, S. Kyoh, S. Maeda, S. Inoue, and K. Nakamae, "Design intention application to tolerance-based manufacturing system," in Proc. SPIE: Design for Manufacturability through Design-Process Integration IV, vol. 7641, 7641-19 (21–25 Feb. 2010).

平成20年度 (2008年度)

  1. A. Yasaka, F. Aramaki, M. Muramatsu, T. Kozakai, O. Matsuda, Y. Sugiyama, T. Doi, O. Takaoka, R. Hagiwara, and K. Nakamae, "Image quality improvement in FIB photomask repair system," in Proc. 52th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, P-4C-02(2 pages), 2008.
  2. A. Yasaka, F. Aramaki, M. Muramatsu, T. Kozakai, O. Matsuda, Y. Sugiyama, T. Doi, O. Takaoka, R. Hagiwara, and K. Nakamae, " Application of vector scanning in FIB photomask repair system," in Proc. 52th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, 9B-4(2 pages), 2008.
  3. A. Takaoka, M. Cao, Y. Midoh, T. Nishida, T. Hasegawa, R. Nishi, Y. Inoue and M. Ogasawara, "Development of automatic system on electron microscopic tomography for 3D medical examination," in Proc. 9th Asia-Pacific Microscopy Conference, Jeju Island, Korea (Nov. 2008).
  4. M. Yamashita, C. Otani, T. Matsumoto, K. Miura, K. Nakamae, M. Tonouchi, K. Nikawa, "Observation of semiconductor test circuits after building-in defect using laser THz emission microscope," 33rd International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz) 2008, pp. 335--336 (Sept. 2008).

平成19年度 (2007年度)

  1. M. Takashima, Y. Midoh, K. Nakamae, "Defect inspection using a high-resolution pattern image obtained from multiple low-resolution images of the same pattern on an observed noisy SEM image," in Proc. SPIE Advanced Lithography: Metrology, Inspection, and Process Control for Microlithography XXII, volume 6922, pp. 692216.1-11 (25-28 February 2008).
  2. T. Mizuno, M. Takahashi, Y. Azuma, H. Yanagita, K. Asayama, and K. Nakamae, " Maximum Permissible EB Acceleration Voltage for SEM-Based Inspection Before Electrical Characterization of Advanced MOS," in Proc. 45th Annual. IEEE International Reliability Physics Symposium, Phoenix, USA, pp. 618-619 (15-19 April 2007).
  3. M. Yamashita, C. Otani, M. Tonouchi, K. Miura, K. Nakamae, K. Nikawa, "THz emission characteristics from LSI-TEG chips under zero bias voltage," in Proc. the Joint 32nd International Conference on Infrared and Millimetre Waves and 15th International Conference on Terahertz Electronics (IRMMW-THz 2007), Cardiff, UK pp. 279-280 (3-7 September 2007).
  4. Y. Midoh, K. Nakamae, and H. Fujioka, "Line edge roughness measurement of nanostructures in SEM metrology by using statistically matched wavelet," in Proc. SPIE: Wavelet Applications in Industrial Processing V, volume 6763, pp. 67630F.1-9 (9-12 October 2007).

平成18年度 (2006年度)

  1. K. Miura, K. Nakamae, K. Nakano, and H. Fujioka, "Study on image-based remote inspection concept," in Proc. 50th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, Baltimore, USA, pp.73-74 (30 May -2 June 2006).
  2. Y. Midoh, K. Nakamae, H. Fujioka, ''A comparison of wavelet multiresolution analysis and scale-space edge detection for lithography metrology, '' in Proc. SPIE: Wavelet Applications in Industrial Processing IV, Boston, USA, vol. 6383 (Oct 2006).
  3. Y. Midoh, M. Nakamura, M. Takashima, K. Nakamae and H. Fujioka, "Computer-assisted lesion detection system for stomach screening using stomach shape and appearance models," in Proc. SPIE: Medical Imaging, San Diego, USA, vol. 6514 (17-22 February 2007).

平成17年度 (2005年度)

  1. K. Miura, M. Fujita, K. Nakamae and H. Fujioka, "Pattern Matching Between an SEM Exposed Pattern Image of LSI Fine Structures and CAD Layout Data by Using the Relaxation Method," in Proc. 49th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Orland, USA, pp. 166-167 (31 May - 3 June 2005).
  2. T. Tominaga, K. Nakamae, T. Matsuo, H. Fujioka, T. Nakasugi, and K. Tawarayama, "Electron-beam direct writing system employing character projection exposure with production dispatching rule," in Proc. 49th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Orland, USA, pp. 297-298 (May 31-June 3, 2005).
  3. R. Suzuki, K. Nakamae, H. Fujioka, "Robustness evaluation of cost-optimum sampling plan for in-line wafer inspection by using Taguchi methods," in Proc. IEEE International Symposium on Semiconductor Manufacturing (ISSM), San Jose, USA, pp. 386-389 (12-15 Sep 2005).
  4. S. Kono, K. Nakamae, M. Nakamura, and H. Fujioka, "Computer-assisted lesion detection system for stomach screening," in Proc. Medical Image Perception Conference XI, Windermere, UK, p. 26 (27-30 Sep 2005).
  5. Y. Yamada, K. Nakamae, H. Fujioka, "Image deblurring by the combined use of a superresolution technique and inverse filtering," in Proc. SPIE: Computational Imaging IV, San Jose, USA, vol. 6065, pp. 416-423 (16-18 Jan 2006).

平成16年度 (2004年度)

  1. T. Matsuo, K. Nakamae, and H. Fujioka, "Operator Headcount Optimization through VLSI Test Process Simulator with Human Factor," in Proc. 15th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC) 2004, Boston, USA, pp. 383-388 (4-6 May 2004).
  2. Y. Midoh, K. Nakamae, and H. Fujioka, "Boundary extraction in the SEM cross section of LSI by multiple Gaussian filtering," in Proc. SPIE: Two- and Three-Dimensional Vision Systems for Inspection, Control, and Metrology II, Philadelphia, USA, 5606, pp. 169-178 (25-28 Oct 2004).
  3. J. Imada, K. Nakamae, M. Chikahisa, and H. Fujioka, "Application of Wavelet analysis to lithography metrology," in Proc. SPIE: Wavelet Applications in Industrial Processing II, Philadelphia, USA, 5607, pp. 15-25 (25-28 Oct 2004).
  4. S. Kohigashi, K. Nakamae, and H. Fujioka, "Image-based computer-assisted diagnosis system for benign paroxysmal positional vertigo," in Proc. SPIE: Image Perception, Observer Performance, and Technology Assessment, San Diego, USA, 5749 (12-17 Feb 2005).

平成15年度 (2003年度)

  1. K. Nakamae, H. Ikeda, and H. Fujioka, "Evaluation of Final Test Process in 64-Mbit DRAM Manufacturing System through Simulation Analysis," in Proc. 14th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC) 2003, Munich, Germany, pp. 202-207 (31 March-1 April 2003).
  2. Y. Zenda, K. Nakamae, and H. Fujioka, "Cost Optimum Embedded DRAM Design by Yield Analysis", in Proc. 2003 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2003), San Jose, USA, pp. 20-24 (28-29 July 2003).
  3. K. Miura, T. Kobatake, K. Nakamae, and H. Fujioka, "A Low Energy FIB Processing, Repair, and Test System," in Proc. 14th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2003), Bordeaux, France, pp. 1627-1631 (7-10 October 2003).
  4. A. Eto, K. Nakamae, and H. Fujioka, "Measurement of Torsional Eye Movement by Spatial Moments of Iris Pattern Image", in Proc. SPIE, Providence, USA, 5261, pp. (28-29 October 2003).

平成14年度 (2002年度)

  1. K. Miura, K. Nakamae, and H. Fujioka, "CAD Navigation System for Backside Waveform Probing of CMOS Devices," in Proc. 13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2002), Rimini, Italy, pp. 1679-1684 (October 7-11, 2002).
  2. Y. Midoh, K. Miura, K. Nakamae, and H. Fujioka, "Fine Structure Measurement in the SEM Cross Section of LSI Using the Canny Edge Detector", in Proc. Proceedings of SPIE Volume: 5011 Machine Vision Applications in Industrial Inspection XI, 5011, pp.190-199 (May 2003).
  3. M. Chikahisa, K. Nakamae, and H. Fujioka, "Estimation of Electron Beam Profile from SEM Image by Using Wavelet," in Proc. SPIE Volume: 5011 Machine Vision Applications in Industrial Inspection XI, 5011, pp.275-282 (May 2003).
  4. K. Nakamae, H. Ikeda, and H. Fujioka, "Evaluation of Final Test Process in 64-Mbit DRAM Manufacturing System through Simulation Analysis," in Proc. 14th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop 2003, pp.202-207 (March 2003).

平成13年度 (2001年度)

  1. K. Miura, K. Nakamae, and H. Fujioka, "Development of an EB/FIB integrated test system," in Proc. 12th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2001), Bordeaux, France, pp. 1489-1494 (October 1-5, 2001).
  2. K. Nakamae, Y. Midoh, K. Miura, and H. Fujioka, “Boundary Extraction in the SEM Cross Section of LSI,” in Proc. SPIE Intelligent Robots and Computer Vision XX: Algorithms, Techniques, and Active Vision, Newton, USA, pp. 451-458 (October 29-31, 2001).

平成12年度 (2000年度)

  1. K. Nakamae, W. Koga, and H. Fujioka, "Effects of Operator Grouping on the VLSI Final Test Facility Layout Scale," in Proc. 11th Annual Advanced Semiconductor Manufacturing Conference and Workshop (ASMC 2000), Boston, USA, pp. 231-236, (September 12-14, 2000).
  2. K. Miura, K. Nakamae, and H. Fujioka, "Automatic EB Fault-Tracing System Using Fuzzy-Logic Approach," in Proc. 11th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2000), Dresden, Germany, pp. 1377-1382, (October 2-6, 2000).
  3. K. Nakamae, A. Itoh, and H. Fujioka, "Fail Pattern Classification and Analysis System of Memory Fail Bit Maps," in Proc. 4th International Conference on Modeling and Simulation of Microsystems, Hilton Head Island, USA, pp. 598-601 (March 19-21, 2001).

平成11年度 (1999年度)以前

  1. Hiromu Fujioka, "Invited: Trends of Electron Beam Testing in Japan," in Proc. 3rd European Conference on Electron and Optical Beam Testing of Integrated Circuits (EOBT), Como, Italy, pp.105-110 (September 9-11, 1991).
  2. H. Fujioka and K. Nakamae, "Invited: New Trends on Beam Testing of Integrated Circuits," in Proc. 4th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, pp.505-512 (October 4-7, 1993).
  3. K. Nakamae, K. Miura and H. Fujioka, "Invited: VLSI Testing with CAD-Linked Electron Beam Test System," in Proc. 5th European Conference on Electron and Optical Beam Testing of Electronic Devices (EOBT), pp.319-330 (September 1995).
  4. H. Fujioka, K. Nakamae and A. Higashi, "Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost," in Proc. International Test Conference (ITC), Washington, D. C., USA, pp.793-799 (October 20-25, 1996).
  5. K. Miura, K. Nakamae and H. Fujioka, "Hierarchical Fault Tracing for VLSI Sequential Circuits from CAD Layout Data in the CAD-Linked EB Test System," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, pp.329-332 (January 28-31, 1997).
  6. A. Chikamura, K. Nakamae and H. Fujioka, "Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in Final Test Process of LSI Manufacturing System," in Proc. IEEE International Symposium on Semiconductor Manufacturing (ISSM'97), pp.D-23-D-26 (October 1997).
  7. K. Miura, K. Nakata, K. Nakamae and H. Fujioka, "Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data," in Proc. 6th Asian Test Symposium (ATS), Akita, Japan, pp. 162-167 (November 17-19, 1997).
  8. M. Sanada and H. Fujioka, "Fault Diagnosis of CMOS LSI with Various Faults by Abnormal IDDQ Phenomenon," in Proc. SPIE Symposium on Microelectronic Manufacturing (SPIE'98), California, USA, pp. 37-46 (September 20-24, 1998).
  9. K. Nakamae, A. Chikamura and H. Fujioka, "Effect of 300mm Wafer and Small Lot Size on Final Test Process Efficiency and Cost of LSI Manufacturing System," in Proc. 9th IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), Boston, USA, pp. 151-155 (September 23-25, 1998).
  10. K. Miura, K. Nakamae and H. Fujioka, "Automatic Fault Tracing by Successive Circuit Extraction from CAD Layout Data with the CAD-Linked EB Test System," in Proc. 9th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Copenhagen, Denmark, pp. 975-980 (October 5-9, 1998).
  11. M. Sanada and H. Fujioka, "Yield Enhancement for Logic LSI by Killer Defect Diagnosis Technique using Abnormal IDDQ Phenomenon," in Proc. 7th International Symposium on Semiconductor Manufacturing (ISSM'98), Tokyo, Japan, pp. 265-268 (October 7-9, 1998).
  12. A. Chikamura, K. Nakamae and H. Fujioka, "Effect of 300mm Wafer and Small Lot Size on Production Dispatching Rule Scheduling and Cost in Final Test Process of LSI Manufacturing System," in Proc. 7th International Symposium on Semiconductor Manufacturing (ISSM'98), Tokyo, Japan, pp. 295-298 (October 7-9, 1998).
  13. H. Fujioka, "Toward High Efficient and Low Cost LSI Manufacturing Test System," in Proc. SEMI Technology Symposium 98, pp.7-19-7-22 (December 2-4, 1998).
  14. K. Nakamae, H. Ohmori, and H. Fujioka, "A Simple Spherical Particle-Induced Yield Predictor," in Proc. 2nd International Conference on Modeling and Simulation of Microsystems, Puerto Rico, USA, pp. 479-482 (April 19-21, 1999).
  15. H. Fujioka, K. Nakamae, A. Chikamura, and M. Kitamura, "TAT- and Cost-reduction Strategies in LSI Manufacturing Test Process," in Proc. 10th annual SEMI/IEEE Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), Boston, USA, pp. 59-63 (September 8-10, 1999).
  16. M. Sanada and H. Fujioka, "Fatal Defect Detection from Visual Abnormalities of Logic LSI Using IDDQ," in Proc SPIE's 1999 Symposium on Microelectronic Manufacturing, Santa Clara, USA, Vol. 3884, pp. 236-247 (September 22-23, 1999).
  17. K. Miura, K. Nakamae, and H. Fujioka, "Intelligent EB Test System for Automatic VLSI Fault Tracing," in Proc. 8th IEEE Asian Test Symposium (ATS'99), Shanghai, China, pp.335-340 (November 16-18, 1999).
  18. K. Nakamae, S. Yamaji, and H. Fujioka, "Wafer Fabrication Process Simulation including Cost: Which should Be Used in An In-Line Wafer Inspection Strategy, High Sensitivity & High Cost Inspection Machine or Low Sensitivity & Low Cost Inspection Machine ?," in Proc. 3rd International Conference on Modeling and Simulation of Microsystems, San Diego, USA, pp. 700-703 (March 27-29, 2000).